LD7577

10

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD7577-DS-01 January 2009

Vcc

UVLO(on)

UVLO(off)

t

t

HV Current

1mA

Startup Current

Vcc current

~ 0mA (off)

Operating Current

(Supply from Auxiliary Winding)

Fig. 14

Current Sensing, Leading-edge Blanking and

the Negative Spike on CS Pin

The typical current mode PWM controller feeds back both

current signal and voltage signal to close the control loop

and to achieve voltage regulation. LD7577 detects the

primary MOSFET current from the CS pin, which is applied

not only for the peak current mode control but also for the

pulse-by-pulse

current

limit.

The

maximum

voltage

threshold of the current sensing pin is set as 0.85V. Thus

the MOSFET peak current can be calculated as:

S

)

MAX

(

PEAK

R

V

85

.

0

I

=

A 250nS leading-edge blanking (LEB) time is incorporated

in the input of CS pin to prevent the false-trigger caused by

any current spike. For low power applications, if the total

pulse width of each turn-on spike is less than 250nS and the

negative spike on the CS pin is not as low as -0.3V, the R-C

filter (as shown in Fig.15) can be eliminated.

Nevertheless,

it is strongly recommended to remain a small R-C filter (as

shown in Fig. 16) for higher power applications to avoid the

CS pin being damaged by negative turn-on spikes.

Output Stage and Maximum Duty-Cycle

An output stage of a CMOS buffer, with typical 500mA

driving capability, is incorporated to drive a power MOSFET

directly.

And the maximum duty-cycle of the LD7577 is

limited to 75% in order to avoid the transformer flux

saturation.

Voltage Feedback Loop

The voltage feedback signal is issued from the TL431 in the

secondary side through the photo-coupler to COMP pin of

the LD7577.

The input stage of the LD7577, like the

UC384X, is incorporated with 2 diodes voltage offset circuit

and a voltage divider with 1/3 ratio.

Therefore,

)

V

2

V

(

3

1

)

V

F

COMP

PWM

(

COMPARATOR

−

×

=

+

A pull-high resistor is embedded internally, eliminating

external corresponding components on a board.

CS

VCC

GND

LD7577

Can be removed if the negative

spike is not over spec. (-0.3V).

OUT

250ns

blanking

time

Fig. 15