MCP3002ISLASHST datasheet(18/34 Pages) MICROCHIP

18 / 34 page

MCP3002

DS21294E-page 18

 2000-2011 Microchip Technology Inc.

FIGURE 6-2:

SPI Communication with the MCP3002 using 8-bit segments (Mode 1,1: SCLK idles

high).

6.2

Maintaining Minimum Clock Speed

When the MCP3002 initiates the sample period, charge

is stored on the sample capacitor. When the sample

period is complete, the device converts one bit for each

clock that is received. It is important for the user to note

that a slow clock rate will allow charge to bleed off the

sample cap while the conversion is taking place. At

85°C (worst case condition), the part will maintain

proper charge on the sample cap for 700 µs at

VDD = 2.7V and 1.5 ms at VDD = 5V. This means that at

VDD = 2.7V, the time it takes to transmit the 1.5 clocks

for the sample period and the 10 clocks for the actual

conversion must not exceed 700 µs. Failure to meet

this criteria may induce linearity errors into the

conversion outside the rated specifications.

6.3

Buffering/Filtering the Analog

Inputs

If the signal source for the A/D Converter is not a low

impedance source, it will have to be buffered or

inaccurate conversion results may occur. It is also

recommended that a filter be used to eliminate any

signals that may be aliased back in to the conversion

results. This is illustrated in Figure 6-3 below where an

op amp is used to drive, filter, and gain the analog input

of the MCP3002. This amplifier provides a low

impedance output for the converter input and a low-

pass filter, which eliminates unwanted high-frequency

noise.

Low-pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab® software. FilterLab

will calculate capacitor and resistors values, as well as,

determine the number of poles that are required for the

application. For more information on filtering signals,

see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

FIGURE 6-3:

Typical Anti-Aliasing Filter

Circuit (2 pole Active Filter).

SCLK

DIN

X = Don’t Care Bits

1112

1314

DOUT

NULL

BIT

HI-Z

MCU latches data from A/D Converter

on rising edges of SCLK

Data is clocked out of

A/D Converter on falling edges

(Null)

MCU Transmitted Data

(Aligned with falling

edge of clock)

MCU Received Data

(Aligned with rising

edge of clock)

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

Start

Bit

MSBF

SGL/

DIFF

ODD/

SIGN

Don’t Care

MCP3002

VDD

10 µF

IN-

IN+

VIN

1µF

MCP601

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