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CC1110-RTR1 数据表(PDF) 60 Page - Texas Instruments |
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CC1110-RTR1 数据表(HTML) 60 Page - Texas Instruments |
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60 / 203 page ![]() CC1110 CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A Page 60 of 202 MEMCTR (0xC7) – Memory Arbiter Control Bit Name Reset R/W Description 7:6 - 00 R0 Not used 5:4 - 01 R/W Not used 3:2 - 00 R0 Not used Flash cache disable. Invalidates contents of instruction cache and forces all instruction read accesses to read straight from flash memory. Disabling will increase power consumption and is provided for debug purposes. 0 Cache enabled 1 CACHDIS 0 R/W 1 Cache disabled 0 - 1 R/W Reserved. Must always be set to 1. |
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