CDP68HC68T1M datasheet(8/24 Pages) INTERSIL

8 / 24 page

FN1547.7

March 17, 2006

Functional Description

The SPI real-time clock consists of a clock/calendar and a

32 x 8 RAM. Communications is established via the SPI

(Serial Peripheral Interface) bus. In addition to the

clock/calendar data from seconds to years, and system

flexibility provided by the 32-byte RAM, the clock features

computer handshaking with an interrupt output and a

separate squarewave clock output that can be one of 7

different frequencies. An alarm circuit is available that

compares the alarm latches with the seconds, minutes and

hours time counters and activates the interrupt output when

they are equal. The clock is specifically designed to aid in

power-down/up applications and offers several pins to aid

the designer of battery backup systems.

Mode Select

The voltage level that is present at the VSYS input pin at the

end of power-on-reset selects the device to be in the single

supply or battery backup mode.

Single-Supply Mode

If VSYS is a logic high when power-on-reset is completed,

CLK OUT, PSE and CPUR will be enabled and the device

will be completely operational. CPUR will be placed low if the

logic level at the VSYS pin goes low. If the output signals

CLK OUT, PSE and CPUR are disabled due to a power-

down instruction, VSYS brought to a logic low and then to a

logic high will re-enable these outputs. An example of the

single-supply mode is where only one supply is available

and VDD, VBATT and VSYS are tied together to the supply.

Battery Backup Mode

If VSYS is a logic low at the end of power-on-reset, CLK

OUT, PSE and CPUR will be disabled (CLK OUT, PSE and

CPUR low). This condition will be held until VSYS rises to a

threshold (about 1.0V) above VBATT. The outputs CLK OUT,

PSE and CPUR will then be enabled and the device will be

operational. If VSYS falls below a threshold above VBATT the

outputs CLK OUT, PSE and CPUR will be disabled. An

example of battery backup operation occurs if VSYS is tied to

VDD and VDD is not connected to a supply when a battery is

connected to the VBATT pin. (See Pin Functions, VBATT for

Battery Backup Operation.)

Clock/Calendar (See Figures 1 and 2)

The clock/calendar portion of this device consists of a long

string of counters that is toggled by a 1Hz input. The 1Hz

input is generated by a prescaler driven by an on-board

oscillator that utilizes one of four possible external crystals or

that can be driven by an external clock source. The 1Hz

trigger to the counters can also be supplied by a 50Hz or

60Hz input source that is connected to the LINE input pin.

The time counters offer seconds, minutes and hours data in

12 hour or 24 hour format. An AM/PM indicator is available

that once set, toggles every 12 hours. The calendar counters

consist of day (day of week), date (day of month), month and

years information. Data in the counters is in BCD format.

The hours counter utilizes BCD for hour data plus bits for

12/24 hour and AM/PM. The 7 time counters are accessed

serially at addresses 20H through 26H. (See Table 1).

RAM

The real-time clock also has a static 32 x 8 RAM that is

located at addresses 00-1FH. Transmitting the

address/control word with bit-5 low selects RAM access. Bits

0 through 4 select the RAM location.

Alarm

The alarm is set by accessing the three alarm latches and

loading the required data. The alarm latches consist of

seconds, minutes and hours registers. When their outputs

equal the values in the seconds, minutes and hours time

counters, an interrupt is generated. The interrupt output will

go low if the alarm bit in the Interrupt Control Register is set

high. The alarm interrupt bit in the Status Register is set

when the interrupt occurs (see Pin Functions, INT Pin). To

preclude a false interrupt when loading the time counters,

the alarm interrupt bit should be set low in the Interrupt

Control Register. This procedure is not required when the

alarm time is set.

Watchdog Function (See Figure 6)

When bit 7 in the Interrupt Control Register is set high, the

Clock’s CE (chip enable) pin must be toggled at a regular

interval without a serial data transfer. If the CE is not toggled,

the clock will supply a CPU reset pulse and bit 6 in the Status

below.

Clock Out

The value in the 3 least significant bits of the Clock Control

(See Clock Control Register). This squarewave signal is

available at the CLK OUT pin. When Power-Down operation

is initiated, the output is set low.

Control Registers and Status Registers

The operation of the Real-Time Clock is controlled by the

Clock Control and Interrupt Control Registers. Both registers

are Read-Write Registers. Another register, the Status

The Status Register is a Read only Register.

Power Control

Power control is composed of two operations, Power Sense

and Power Down/Up. Two pins are involved in power

sensing, the LINE input pin and the INT output pin. Two

additional pins are utilized during power-down/up operation.

They are the PSE (Power Supply Enable) output pin and

VSYS input pin.

50Hz

60Hz

XTAL

MIN

MAX

MIN

MAX

MIN

MAX

Service Time

10ms

8.3ms

7.8ms

Reset Time

40ms

16.7

33.3ms

15.6

31.3ms

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