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HEF4040B 数据表(PDF) 4 Page - NXP Semiconductors

部件名 HEF4040B
功能描述  12-stage binary counter
PDF  5 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

HEF4040B 数据表(HTML) 4 Page - NXP Semiconductors

  HEF4040B Datasheet HTML 1Page - NXP Semiconductors HEF4040B Datasheet HTML 2Page - NXP Semiconductors HEF4040B Datasheet HTML 3Page - NXP Semiconductors HEF4040B Datasheet HTML 4Page - NXP Semiconductors HEF4040B Datasheet HTML 5Page - NXP Semiconductors  
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January 1995
4
Philips Semiconductors
Product specification
12-stage binary counter
HEF4040B
MSI
Note
1. For other loads than 50 pF at the nth output, use the slope given.
Minimum clock
5
50
25
ns
see also waveforms
Fig.4
pulse width; HIGH
10
tWCPH
30
15
ns
15
20
10
ns
Minimum MR
5
40
20
ns
pulse width; HIGH
10
tWMRH
30
15
ns
15
20
10
ns
Recovery time
5
40
20
ns
for MR
10
tRMR
30
15
ns
15
20
10
ns
Maximum clock
5
10
20
MHz
pulse frequency
10
fmax
15
30
MHz
15
25
50
MHz
VDD
V
TYPICAL FORMULA FOR P (
µW)
Dynamic power
5
400 fi +∑ (foCL) × VDD2
where
dissipation per
10
2 000 fi +∑ (foCL) × VDD2
fi = input freq. (MHz)
package (P)
15
5 200 fi +∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (f
oCL) = sum of outputs
VDD = supply voltage (V)
VDD
V
SYMBOL
MIN. TYP. MAX.
TYPICAL EXTRAPOLATION
FORMULA



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