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Device Address

0

1

1

1

A1

A2

A0

Slave Address

R/W

Fixed

Hardware

Selectable

Control Register and Command Byte

0

0

0

0

B1

B0

0

0

PCA9554A

WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

SCPS127A – SEPTEMBER 2006 – REVISED FEBRUARY 2007

Figure 4 shows the address byte for the PCA9554A.

Figure 4. PCA9554A Address

Address Reference

INPUTS

A2

A1

A0

L

L

L

56 (decimal), 38 (hexadecimal)

L

L

H

57 (decimal), 39 (hexadecimal)

L

H

L

58 (decimal), 3A (hexadecimal)

L

H

H

59 (decimal), 3B (hexadecimal)

H

L

L

60 (decimal), 3C (hexadecimal)

H

L

H

61 (decimal), 3D (hexadecimal)

H

H

L

62 (decimal), 3E (hexadecimal)

H

H

H

63 (decimal), 3F (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read

is selected. A low (0) selects a write operation.

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the PCA9554A. Two bits of this command byte state the operation (read or write)

and the internal register (input, output, polarity inversion or configuration) that will be affected. This register can

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until

a new command byte has been sent.

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE

POWER-UP

REGISTER

PROTOCOL

(HEX)

DEFAULT

B1

B0

0

0

0x00

Input Port Register

Read byte

XXXX XXXX

0

1

0x01

Output Port Register

Read/write byte

1111 1111

1

0

0x02

Polarity Inversion Register

Read/write byte

0000 0000

1

1

0x03

Configuration Register

Read/write byte

1111 1111

7

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