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HEF4528BF 数据表(PDF) 2 Page - NXP Semiconductors

部件名 HEF4528BF
功能描述  Dual monostable multivibrator
PDF  8 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

HEF4528BF 数据表(HTML) 2 Page - NXP Semiconductors

  HEF4528BF Datasheet HTML 1Page - NXP Semiconductors HEF4528BF Datasheet HTML 2Page - NXP Semiconductors HEF4528BF Datasheet HTML 3Page - NXP Semiconductors HEF4528BF Datasheet HTML 4Page - NXP Semiconductors HEF4528BF Datasheet HTML 5Page - NXP Semiconductors HEF4528BF Datasheet HTML 6Page - NXP Semiconductors HEF4528BF Datasheet HTML 7Page - NXP Semiconductors HEF4528BF Datasheet HTML 8Page - NXP Semiconductors  
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January 1995
2
Philips Semiconductors
Product specification
Dual monostable multivibrator
HEF4528B
MSI
DESCRIPTION
The HEF4528B is a dual retriggerable-resettable
monostable multivibrator. Each multivibrator has an active
LOW input (I0), and active HIGH input (I1), an active LOW
clear direct input (CD), an output (O) and its complement
(O), and two pins for connecting the external timing
components (CTC(1), RCTC).
An external timing capacitor (Ct ) must be connected
between CTC and RCTC and an external resistor (Rt) must
be connected between RCTC and VDD. The duration of the
(1) Always connected to ground.
output pulse is determined by the external timing
components Ct and Rt.
A HIGH to LOW transition on I0 when I1 is LOW or a LOW
to HIGH transition on I1 when I0 is HIGH produces a
positive pulse (LOW-HIGH-LOW) and O and a negative
pulse (HIGH-LOW-HIGH) on O if the CD is HIGH. A LOW
on CD forces O LOW, O HIGH and inhibits any further
pulses until CD is HIGH.
Fig.1 Functional diagram.
PINNING
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
HEF4528BP(N):
16-lead DIL; plastic (SOT38-1)
HEF4528BD(F):
16-lead DIL; ceramic (cerdip) (SOT74)
HEF4528BT(D):
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
I0A, I0B
input (HIGH to LOW triggered)
I1A, I1B
input (LOW to HIGH triggered)
CDA, CDB
clear direct input (active LOW)
OA, OB
output
OA, OB
complementary output (active LOW)
CTC A, CTC B
external capacitor connections (1)
RCTC A,
external capacitor/ resistor connections
RCTC B
Fig.2 Pinning diagram.



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