4

FN3020.7

July 28, 2005

Test Circuits

FIGURE 1. GENERAL TEST CIRCUIT

FIGURE 2. POWER-OFF SOURCE RESISTANCE

CONFIGURATION

Typical Performance Curves

FIGURE 4. V+, V- OUTPUT VOLTAGES vs LOAD CURRENT

Pin Descriptions

PDIP, CERDIP

SOIC

PIN NAME

DESCRIPTION

1

1

C1+

External capacitor “+” for internal voltage doubler.

2

2

V+

Internally generated +10V (typical) supply.

3

3

C1-

External capacitor “-” for internal voltage doubler.

4

4

C2+

External capacitor “+” internal voltage inverter.

5

5

C2-

External capacitor “-” internal voltage inverter.

6

6

V-

Internally generated -10V (typical) supply.

77

RS-232 Transmitter 2 output

±10V (typical).

88

RS-232 Receiver 2 input, with internal 5K pulldown resistor to GND.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

C1+

V+

C1-

C2+

C2-

V-

GND

+4.5V TO

+5.5V INPUT

3k

Ω

T1 OUTPUT

RS-232

±30V INPUT

TTL/CMOS

OUTPUT

TTL/CMOS

INPUT

TTL/CMOS

INPUT

TTL/CMOS

OUTPUT

+

-

1

µF

C3

+

-

1

µF

C1

+

-

1

µF

C2

1

µF C4

3k

Ω

T2 OUTPUT

RS-232

±30V INPUT

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

C1+

V+

C1-

C2+

C2-

V-

GND

A

550

500

450

400

350

300

250

200

150

34

56

V- SUPPLY

V+ SUPPLY

OPERATING

RANGE

GUARANTEED

EXTERNAL SUPPLY LOAD

1k

Ω BETWEEN V+ + GND

OR V- + GND

TRANSMITTER OUTPUT

OPEN CIRCUIT

10

TRANSMITTER OUTPUTS

OPEN CIRCUIT

9

8

7

6

5

4

3

2

1

0

3

10

9

8

7

6

5

4

ICL232

ICL232