9.3 Layout

9.3.1 Layout Guidelines

• Place the power-supply bypass capacitor as close as possible to the supply and ground pins. The

recommended value of this bypass capacitor is from 0.1 μF to 10 μF. If necessary, additional decoupling

capacitance can be added to compensate for noisy or high-impedance power supplies. The smallest

capacitor must be placed closest to the device.

• The output must be decoupled with a 1 μF to 100 μF low ESR (maximum 1 Ω) capacitor.

• Place a 1 μF to 100 μF low leakage noise filtering capacitor between the NR pin and ground.

9.3.2 Layout Example

Figure 9-6. Layout Example for SOIC package

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SNVSCN7 – NOVEMBER 2023

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