AM29F040B_06 datasheet(13/36 Pages) AMD

13 / 36 page

November 1, 2006 21445E5

Am29F040B

D A TA

SH EE T

Any commands written to the device during the Em-

bedded Program Algorithm are ignored.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. However, a succeeding read shows that the

data is still “0”. Only erase operations can convert a “0”

to a “1”.

Note: See the appropriate Command Definitions table for

program command sequence.

Figure 1.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored.

The system can determine the status of the erase op-

eration by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits.

When the Embedded Erase algorithm is complete, the

device returns to reading array data and addresses are

no longer latched.

Figure 2 illustrates the algorithm for the erase opera-

tion. See the Erase and Program Operations tables in

“AC Characteristics” for parameters, and to the Chip/

Sector Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two un-

lock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector

erase command. The Command Definitions table

shows the address and data requirements for the sec-

tor erase command sequence.

The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-

rithm automatically programs and verifies the sector for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or tim-

ings during these operations.

After the command sequence is written, a sector erase

time-out of 50 µs begins. During the time-out period,

additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer

may be done in any sequence, and the number of sec-

tors may be from one sector to all sectors. The time

between these additional cycles must be less than 50

µs, otherwise the last address and command might not

be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during

this time to ensure all commands are accepted. The in-

terrupts can be re-enabled after the last Sector Erase

command is written. If the time between additional sec-

tor erase commands can be assumed to be less than

50 µs, the system need not monitor DQ3. Any com-

mand other than Sector Erase or Erase Suspend

during the time-out period resets the device to

reading array data. The system must rewrite the com-

mand sequence and any additional sector addresses

and commands.

The system can monitor DQ3 to determine if the sector

erase timer has timed out. (See the “DQ3: Sector Erase

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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