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AM29DS323D 数据表(PDF) 39 Page - Advanced Micro Devices |
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AM29DS323D 数据表(HTML) 39 Page - Advanced Micro Devices |
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39 / 56 page  October 10, 2006 23480A5 Am29DS323D 37 D A TA SH EE T AC CHARACTERISTICS Memory Array Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 16 for test specifications. 3. For data polling and toggle bit specifications, see “Data Polling and Toggle Bit” on page 44. Parameter Description Test Setup 110 120 JEDEC Std Unit t AVAV t RC Read Cycle Time (Note 1) Min 110 120 ns t AVQV t ACC Address to Output Delay CE#, OE# = V IL Max 110 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 110 120 ns tGLQV tOE Output Enable to Output Delay Max 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns t AXQX t OH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time, Read Array (Note 1) Min 0 ns tOH tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH 0 V RY/BY# RESET# tDF Figure 13. Read Operation Timings |
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