AM29PL320D datasheet(22/49 Pages) AMD

22 / 49 page

Am29PL320D

June 13, 2005

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 13 shows the address and data requirements.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect mode,

and the system may read any number of autoselect

codes without reinitiating the command sequence.

Tables 13 and 14 show the address and data require-

ments for the command sequence. To determine sec-

tor protection information, the system must write to the

appropriate sector address (SA). Tables 4 and 6 show

the address range associated with each sector.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Enter SecSi

™ Sector/Exit SecSi Sector

Command Sequence

The SecSi Sector region provides a secured data area

containing a random, eight-word (or four double word)

electronic serial number (ESN). The system can ac-

cess the SecSi Sector region by issuing the three-

cycle Enter SecSi Sector command sequence. The

device continues to access the SecSi Sector region

until the system issues the four-cycle Exit SecSi Sec-

tor command sequence. The Exit SecSi Sector com-

mand s equ enc e ret u r n s the dev ic e to nor m a l

operation. Table 13 shows the address and data re-

quirements for both command sequences. See also

“S ec Si

™ (Se cu red S ilicon) Sector Fla sh

Memory Region” for further information.

Word/Double Word Program

Command Sequence

The system may program the device by word or double

word, depending on the state of the WORD# input.

Programming is a four-bus-cycle operation. The pro-

gram command sequence is initiated by writing two

unlock write cycles, followed by the program set-up

command. The program address and data are written

next, which in turn initiate the Embedded Program al-

gorithm. The system is not required to provide further

controls or timings. The device automatically gener-

ates the program pulses and verifies the programmed

cell margin. Table 13 shows the address and data re-

quirements for the program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the program operation by using

DQ7 or DQ6. See “Write Operation Status” for informa-

tion on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. The Program

command sequence should be reinitiated once the de-

vice has reset to reading array data, to ensure data

integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempting to do so may

halt the operation and set DQ5 to “1,” or cause the

Data# Polling algorithm to indicate the operation was

successful. However, a succeeding read will show that

the data is still “0”. Only erase operations can convert

a “0” to a “1”.

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to pro-

gram bytes or words to the device faster than using the

standard program command sequence. The unlock by-

pass command sequence is initiated by first writing

two unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. The de-

vice then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the pro-

gr am addres s and data. Addit i onal da t a is

programmed in the same manner. This mode dis-

penses with the initial two unlock cycles required in the

standard program command sequence, resulting in

faster total programming time. Table 13 shows the re-

quirements for the command sequence.

During the unlock bypass mode, only the Unlock By-

pass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset com-

mand sequence. The first cycle must contain the data

90h; the second cycle the data 00h. Addresses are

don’t care for both cycles. The device then returns to

reading array data.

Figure 2 illustrates the algorithm for the program oper-

ation. See the Program/Erase Operations table in “AC

Characteristics” for parameters, and to Figure 17 for

timing diagrams.

AM29PL320D 数据表(PDF) 22 Page - Advanced Micro Devices

AM29PL320D 数据表(HTML) 22 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

数据表下载