AM29BDS640G datasheet(29/77 Pages) AMD

29 / 77 page

May 9, 2006 25903C2

Am29BDS640G

Data

Sheet

Figure 1. Synchronous/Asynchronous State Diagram

Read Mode Setting

On power-up or hardware reset, the device is set to be in asynchronous read

mode. This setting allows the system to enable or disable burst mode during sys-

tem operations. Address A19 determines this setting: “1’ for asynchronous mode,

“0” for synchronous mode.

Programmable Wait State Configuration

The programmable wait state feature informs the device of the number of clock

cycles that must elapse after AVD# is driven active before data will be available.

This value is determined by the input frequency of the device. Address bits A14–

A12 determine the setting (see Table 8).

The wait state command sequence instructs the device to set a particular number

of clock cycles for the initial access in burst mode. The number of wait states that

should be programmed into the device is directly related to the clock frequency.

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(A19 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(A19 = 1)

AM29BDS640G 数据表(PDF) 29 Page - Advanced Micro Devices