M49000000S datasheet(13/64 Pages) AMD

13 / 64 page

Am49DL32xBG

July 19, 2002

P R E L I M I NARY

FLASH DEVICE BUS OPERATIONS

Word/Byte Configuration

The CIOf pin controls whether the device data I/O pins

operate in the byte or word configuration. If the CIOf

pin is set at logic ‘1’, the device is in word configura-

tion, DQ15–DQ0 are active and controlled by CE#f

and OE#.

If the CIOf pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ7–DQ0 are

active and controlled by CE#f and OE#. The data I/O

pins DQ14–DQ8 are tri-stated, and the DQ15 pin is

used as an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE#f and OE# pins to V

IL. CE#f is the power

control and selects the device. OE# is the output con-

trol and gates array data to the output pins. WE#

should remain at V

IH . The C I Of pin determines

whether the device outputs array data in words or

bytes.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory

content occurs during the power transition. No com-

mand is necessary in this mode to obtain array data.

Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid

data on the device data outputs. Each bank remains

enabled for read access until the command register

contents are altered.

Refer to the Flash Read-Only Operations table for tim-

ing specifications and to Figure 14 for the timing dia-

gram. I

CC1 in the DC Characteristics table represents

the active current specification for reading array data.

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE#f to V

IL, and OE# to VIH.

For program operations, the CIOf pin determines

whether the device accepts program data in bytes or

words. Refer to “Flash Device Bus Operations” for

more information.

The device features an Unlock Bypass mode to facil-

itate faster programming. Once a bank enters the Un-

lock Bypass mode, only two write cycles are required

to program a word or byte, instead of four. The

“Byte/Word Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command se-

quences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 3 indicates the address

space that each sector occupies. Similarly, a “sector

address” is the address bits required to uniquely select

a sector. The “Flash Command Definitions” section

has details on erasing a sector or the entire chip, or

suspending/resuming the erase operation.

The device address space is divided into four banks. A

“bank address” is the address bits required to uniquely

select a bank.

CC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The Flash

AC Characteristics section contains timing specifica-

tion tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This is one of two functions

provided by the WP#/ACC pin. This function is prima-

rily intended to allow faster manufacturing throughput

at the factory.

If the system asserts V

HH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors,

and uses the higher voltage on the pin to reduce the

time required for program operations. The system

would use a two-cycle program command sequence

as required by the Unlock Bypass mode. Removing

HH from the WP#/ACC pin returns the device to nor-

mal operation. Note that V

HH must not be asserted on

WP#/ACC for operations other than accelerated pro-

gramming, or device damage may result. In addition,

the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

See “Write Protect (WP#)” on page 19 for related in-

formation.

Autoselect Functions

If the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ15–DQ0. Standard read cycle timings apply in

this mode. Refer to the Autoselect Mode and Autose-

lect Command Sequence sections for more informa-

tion.

Simultaneous Read/Write Operations with

Zero Latency

This device is capable of reading data from one bank

of memory while programming or erasing in the other

bank of memory. An erase operation may also be sus-

pended to read from or program to another location

within the same b ank (except the sector bein g

erased). Figure 21 shows how read and write cycles

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