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USB2005 数据表(PDF) 11 Page - SMSC Corporation

部件名 USB2005
功能描述  USB 2.0 ATA/ATAPI Controller with PD-DRM
PDF  21 Pages
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制造商  SMSC [SMSC Corporation]
网页  http://www.smsc.com
标志 SMSC - SMSC Corporation

USB2005 数据表(HTML) 11 Page - SMSC Corporation

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USB 2.0 ATA/ATAPI Controller with PD-DRM
Datasheet
SMSC USB2005
11
Revision 0.2 (01-16-07)
DATASHEET
Termination Resistor
RTERM
A precision 1.5Kohm precision resistor is
attached to this pin from a 3.3V supply.
Full Speed USB
Data
FS-
FS+
IO-U
These pins connect to the USB- and USB+
pins through 31.6 ohm series resistors.
MEMORY/IO INTERFACE
Memory Data Bus
MD[7:0]
IO12PU
When ROMEN=0, these signals are used to
transfer data between the internal CPU and the
external program memory. When ROMEN=1, a
weak internal pull up is activated to prevent
these pins from floating.
Memory Address
Bus
MA[15:0]
O12
These signals address memory locations within
the external memory.
Memory Write Strobe
nMWR
O12
Program Memory Write; active low
Memory Read
Strobe
nMRD
O12
Program Memory Read; active low
IO Read Strobe
nIOR
O12
XDATA space Read; active low
IO Write Strobe
nIOW
O12
XDATA space Write; active low
MISC
Crystal
Input/External Clock
Input
XTAL1/
CLKIN
ICLKx
12Mhz Crystal or external clock input.
This pin can be connected to one terminal of
the crystal or can be connected to an external
12Mhz clock when a crystal is not used.
Crystal Output
XTAL2
OCLKx
12Mhz Crystal
This is the other terminal of the crystal, or left
open when an external clock source is used to
drive XTAL1/CLKIN. It may not be used to
drive any external circuitry other than the
crystal circuit.
Clock Output
CLKOUT
O8
This pin produces a 30Mhz clock signal
independent of the processor clock divider. It is
held inactive and low whenever the internal
processor clock is stopped or is being obtained
from the ring oscillator.
Internal ROM Enable
ROMEN
IP
When left unconnected or tied high, the
USB97C202 uses the internal ROM for
program execution. When tied low, an external
program memory should be connected to the
memory/data bus. The state of this pin latched
internally on the rising edge of nRESET.
Table 5.1 USB2005 Pin Descriptions (continued)



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