LTC7825

13

Rev. A

For more information www.analog.com

VOLTAGE DOUBLER AND INVERTER APPLICATIONS

The LTC7825 may be used as a voltage doubler or volt-

age inverter. In voltage doubler applications, VLOW is the

input and VHIGH is the output. In voltage inverter applica-

tions, VHIGH is the input, VLOW is the ground and PGND is

the negative output. In the doubler and inverter applica-

tions, the LTC7825 can start-up without capacitor inrush

charging current if the input voltage is ramping slowly up

from zero. As long as the input voltage ramps up slowly

(in milliseconds), the output voltage can track the input

voltage and the voltage difference between capacitors is

always small, minimizing inrush current. Slew rate control

of the input voltage can be achieved by using a discon-

nect MOSFET at the input or using Hot Swap controllers.

Unlike voltage dividers, the voltage doubler and inverter

applications have to start up from zero input voltage every

time, but they can start up with heavy initial load currents.

INPUT/OUTPUT CAPACITOR AND FLYING CAPACITOR

SELECTION

In high power switched capacitor applications, large AC

currents flow through the flying capacitors and input/out-

put capacitors. Low ESR ceramic capacitors are highly

recommended for high power switched capacitor applica-

tions. Make sure the maximum RMS capacitor current is

within the spec or higher rated capacitors are preferred.

Note that capacitor manufacturers’ ripple current ratings

are often based on only 2000 hours of life. This makes

it advisable to further derate the capacitor, or to choose

capacitors rated at a higher temperature than required.

Several capacitors may be paralleled to meet size or

height requirements in the design.

The input capacitor RMS current is approximately half of

the load current. The input capacitor has to be selected to

accommodate the maximum load conditions.

PC BOARD LAYOUT CHECKLIST

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC.

1. Are the exposed pad SGND/VLOW/VOUT solidly con-

nected to the corresponding pins on the PCB?

2. Are all the capacitors CFLY/CLOW/COUT close to the IC?

The PCB trace to those capacitors should be wide

enough to handle large load currents.

3. Is the INTVCC bypassing capacitor connected close to

the IC, between the INTVCC and ground plane?

4. Are the PCB traces to VHIGH/VLOW/PGND wide enough

to handle large load currents?

5. In the cases of a multilayer board, are there enough

thermal vias on the VHIGH/VOUT/PGND plane?

Refer to the standard demo board design on here for the

PCB layout examples.

APPLICATIONS INFORMATION

78251 F05

FAULT

LOW

4µA CHARGE

TIMER PIN

4µA CHARGE

TIMER PIN

8µA CHARGE

TIMER PIN

0.5V

1.0V

3V

PRE-BALANCE TIME

FAULT

RELEASE

Figure 2. Timer Behavior During Fault or Start-Up