2

FN6462.0

February 26, 2007

Ordering Information

PART NUMBER

PART MARKING

TEMP. RANGE (°C)

PACKAGE

PKG. DWG. #

PX3511ADAG (Note)

PX3511 ADAG

0 to +85

8 Ld SOIC (Pb-free)

M8.15

PX3511ADAG-R3 (Note)

PX3511 ADAG

0 to +85

8 Ld SOIC (Pb-free) Tape and Reel

M8.15

PX3511ADDG

11AD

0 to +85

10 Ld 3x3 DFN

L10.3x3

PX3511ADDG-RA

11AD

0 to +85

10 Ld 3x3 DFN Tape and Reel

L10.3x3

PX3511BDAG (Note)

PX351 BDAG

0 to +85

8 Ld SOIC (Pb-free)

M8.15

PX3511BDAG-R3 (Note)

PX3511 BDAG

0 to +85

8 Ld SOIC (Pb-free) Tape and Reel

M8.15

PX3511BDDG

11BD

0 to +85

10 Ld 3x3 DFN

L10.3x3

PX3511BDDG-RA

11BD

0 to +85

10 Ld 3x3 DFN Tape and Reel

L10.3x3

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts

PX3511ACB, PX3511BCB

(8 LD SOIC)

TOP VIEW

PX3511ACR, PX3511BCR

(10 LD 3x3 DFN)

TOP VIEW

UGATE

BOOT

PWM

GND

1

2

3

4

8

7

6

5

PHASE

PVCC

VCC

LGATE

1

2

3

4

5

9

8

7

6

10

USB

PPR

CHG

NTC or OVP

USBP

IUSB

ICDL

GND

BAT

or EN

CRD L

UGATE

BOOT

N/C

GND

PHASE

PW M

PVCC

N/C

VCC

LGATE

Block Diagram

PX3511A AND PX3511B

PVCC

VCC

PWM

+5V

10K

8K

BOOT

UGATE

PHASE

LGATE

GND

FOR DFN -DEVICES, THE PAD ON THE BOTTOM SIDE OF

PAD

THE PACKAGE MUST BE SOLDERED TO THE CIRCUIT’S GROUND.

UVCC = VCC FOR PX3511A

CONTROL

LOGIC

POR/

SHOOT-

THROUGH

PROTECTION

Pre-POR OVP

(LVCC)

UVCC = PVCC FOR PX3511B

UVCC

FEATURES

PX3511A, PX3511B