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N

CLK

D

OVR

[11:0],

N+1

N+5

t

CLKL

t

DRY

t

DATA

t

CLKH

t

a

D[11:0], OVR

CLK

N+2

N+3

N+4

DRY

DRY

N

N+1

N–1

Sample

N–1

T0158-01

Latency = 3.5 Clock Cycles

TIMING CHARACTERISTICS

(1)

ADS5463

SLAS515 – NOVEMBER 2006

Figure 1. Timing Diagram

Typical values at T

500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-V

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

200

ps

Aperture jitter, rms

160

fs

Latency

3.5

cycles

Clock period

2

50

ns

Clock pulse duration, high

1

ns

Clock pulse duration, low

1

ns

Zero crossing, 7-pF differential loading

800

1100

1400

ps

Zero crossing, 7-pF differential loading

600

1100

1600

ps

DATA to DRY skew

–350

0

350

ps

DRY/DATA/OVR rise time

7-pF differential loading

500

ps

DRY/DATA/OVR fall time

7-pF differential loading

500

ps

(1)

Timing parameters are assured by design or characterization, but not production tested.

(2)

delay.

6

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