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TIMING REQUIREMENTS

CDCVF855

SCAS839A – APRIL 2007 – REVISED MAY 2007

ELECTRICAL CHARACTERISTICS (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

65

80

Without load

75

90

110

140

Differential outputs terminated

mA

with 120

Ω, C

120

150

130

160

Differential outputs terminated

with 120

Ω, C

140

170

Part-to-part input capacitance

∆C

1

pF

variation

Input capacitance difference

between CLK and CLK, FBIN

0.25

pF

and FBIN

over recommended ranges of supply voltage and operating free-air temperature

PARAMETER

MIN

MAX

UNIT

Operating clock frequency

60

220

MHz

Application clock frequency

90

220

Input clock duty cycle

40%

60%

10

µs

30

ns

(1)

The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be

the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This

parameter does not apply for input modulation under SSC application.

(2)

5

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