Philips Semiconductors

Product specification

PCA8550

1998 Sep 29

3

PIN DESCRIPTION

PIN

NUMBER

SYMBOL

FUNCTION

1

2

3

OVERRIDE#

Forces all outputs to logic 0

4

MUX_IN A

5

MUX_IN B

External inputs to multiplexer

6

MUX_IN C

External in uts to multi lexer

7

MUX_IN D

8

GND

Common ground voltage rail

9

MUX_OUT D

10

MUX_OUT C

2 5V multiplexed output

11

MUX_OUT B

2.5V multi lexed out ut

12

MUX_OUT A

13

MUX_SELECT

Selects MUX_IN inputs or

register contents for

MUX_OUT outputs

14

NON_MUXED_OUT

TTL-level output from

non-volatile memory

15

WP

Non-volatile register

write-protect

16

Positive voltage rail

FUNCTION TABLE

Table 1. Function table

OVERRIDE

#

MUX_SELECT

MUX_OUT

OUTPUTS

NON_MUXED_OUT

OUTPUT

0

0

All 0’s

All 0’s

0

1

MUX_IN

inputs

Latched

1

0

From non-

volatile

register

From non-volatile

register

1

1

MUX_IN

inputs

From non-volatile

register

NOTE

1. Latched NON_MIXED_OUT state will be the value present on

the NON_MUXED_OUT output at the time of the MUX_SELECT

input transitioned from a logic 0 to a logic 1 state.

value followed by a 1-bit read/write value which determines the direction of the data transfer.

SW00218

MSB

LSB

11

1

0

R/W#

10

0

Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write

data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read

from the register if the bit is logic 1. The three high-order bits (see FIgure 2) are logic 0. The next bit is data which is non-multiplexed. The low

four bits are the data which will be multiplexed. A write with any of the first three bits non-zero will be aborted.

NOTE:

component is dropped below normal operating levels.