PCA9559PW datasheet(2/11 Pages) PHILIPS

2 / 11 page

Philips Semiconductors

Product data

PCA9559

5-bit multiplexed/1-bit latched 6-bit

I2C EEPROM DIP switch

2003 Jun 27

FEATURES

• 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch

• 6-bit internal non-volatile register

• Internal non-volatile register programmable and readable via

I2C-bus

• Override input forces all outputs to logic 0

• 5 open drain multiplexed outputs

• 1 open drain non-multiplexed (latched) output

• 5 V and 2.5 V tolerant inputs

• Useful for ‘jumperless’ configuration of PC motherboards

• 2 address pins, allowing up to 4 devices on the I2C-bus

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

DESCRIPTION

The PCA9559 is a 20-pin CMOS device consisting of one 6-bit

non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit

multiplexed output with one latched EEPROM bit. It is used for DIP

switch-free or jumper-less system configuration and supports Mobile

and Desktop VID Configuration, where 2 preset values (1 set of

internal non-volatile registers and 1 set of external hardware pins)

set processor voltage for operation in either performance or deep

sleep modes. The PCA9559 is also useful in server and

telecom/networking applications when used to replace DIP switches

or jumpers, since the settings can be easily changed via I2C/SMBus

without having to power down the equipment to open the cabinet.

The non-volatile memory retains the most current setting selected

before the power is turned off.

The PCA9559 typically resides between the CPU and Voltage

Regulator Module (VRM) when used for CPU VID (Voltage

IDentification code) configuration. It is used to bypass the

CPU-defined VID values and provide a different set of VID values to

the VRM, if an increase in the CPU voltage is desired. An increase

in CPU voltage combined with an increase in CPU frequency leads

to a performance boost of up to 7.5%. Lower CPU voltage reduces

power consumption.

The PCA9559 has 2 address pins allowing up to 4 devices to be

placed on the same I2C-bus or SMBus.

PIN CONFIGURATION

I2C SCL

I2C SDA

MUX_IN B

VCC

MUX_IN C

MUX_IN D

MUX_IN E

MUX_OUT B

MUX_OUT C

MUX_OUT D

MUX_OUT E

SW00216

GND

NON_MUXED_OUT

MUX_OUT A

MUX_IN A

OVERRIDE_N

MUX_SELECT

Figure 1. Pin configuration

PIN DESCRIPTION

NUM-

BER

SYMBOL

FUNCTION

I2C SCL

Serial I2C-bus clock

I2C SDA

Serial bi-directional I2C-bus data

A1 Address

A0 Address

5-9

MUX_IN A-E

External inputs to multiplexer

GND

Ground

MUX_SELECT

Selects MUX_IN inputs or register

contents for MUX_OUT outputs

12-16

MUX_OUT E-A

Open drain multiplexed outputs

NON_MUXED_

OUT

Open drain outputs from

non-volatile memory

OVERRIDE_N

Forces all outputs to logic 0

Non-volatile register write-protect

VCC

Power supply: +3.0 to +3.6 V

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

20-Pin Plastic TSSOP

0 to +70

°C

PCA9559PW

PCA9559

SOT360-1

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

PCA9559PW 数据表(PDF) 2 Page - NXP Semiconductors

PCA9559PW 数据表(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11

数据表下载