Philips Semiconductors

PCD3316

CIDCW receiver

Product specification

11 March 1999

16 of 30

9397 750 04824

© Philips Electronics N.V. 1999. All rights reserved.

7.13.2

FSK data register (CDFSK)

7.13.3

Status register (CIDSTA)

7.13.4

Ringer period register (CIDRNG)

Table 7:

Interrupt register

Address: 01H; read only.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Table 8:

Description of CDFSK bits

Bit

Symbol

Description

CDFSK.7 to

CDFSK.0

D7 to D0

If an FSK interrupt has occurred and no FSK error is detected, the FSK data register

contains valid data.

Table 9:

Status register

Address: 02H; read only.

7

6

5

4

3

2

1

0

POL1

POL0

LOW-BAT Indication

FSK-BOM Indication

FSK-OVR Error

FSK-FRM Error

−−

Table 10: Description of CIDSTA bits

Bit

Symbol

Description

CIDSTA.7

POL1

CIDSTA.6

POL0

CIDSTA.5

CIDSTA.4

FSK-BOM Indication FSK-BOM Indication = 0: begin of mark period not yet detected;

FSK-BOM Indication = 1: begin of mark period detected

CIDSTA.3

FSK-OVR Error

FSK-OVR Error = 0: no FSK overrun error;

FSK-OVR Error = 1: FSK overrun error, data byte(s) lost

CIDSTA.2

FSK-FRM Error

FSK-FRM Error = 0: no FSK frame error;

FSK-FRM Error = 1: FSK frame error, stop bit was wrong

CIDSTA.1 and

CIDSTA.0

−

reserved bits

Table 11: Register format

Address: 03H; read only.

7

6

5

4

3

2

1

0

D7

D6

D5

D4

D3

D2

D1

D0

Table 12: Description of CIDRNG bits

Bit

Symbol

Description

CIDRNG.7 to

CIDRNG.0

D7 to D0

The value held in this byte denotes the time between two positive edges of the POL1

comparator output (between two positive edges of POL1 one positive edge of POL0

must have been detected).