PCD3755AP datasheet(18/32 Pages) PHILIPS

18 / 32 page

1997 Apr 16

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers with DTMF generator,

8 kbytes OTP and 128 bytes EEPROM

PCD3755A; PCD3755E;

PCD3755F

DERIVATIVE INTERRUPTS

One derivative interrupt event is defined. It is controlled by

bits T2F and ET2I in the EPCR (see Tables 10 and 11).

The derivative interrupt event occurs when T2F is set. This

request is honoured under the following circumstances:

• No interrupt routine proceeds

• No external interrupt request is pending

• The derivative interrupt is enabled

• ET2I is set.

The derivative interrupt routine must include instructions

that will remove the cause of the derivative interrupt by

explicitly clearing T2F. If the derivative interrupt is not

used, T2F may directly be tested by the program.

Obviously, T2F can also be asserted under program

control, e.g. to generate a software interrupt.

TIMING

Although thePCD3755A, PCD3755E and PCD3755F

operate over a clock frequency range from 1 to 16 MHz,

fxtal = 3.58 MHz will usually be chosen to take full

advantage of the frequency generator section.

10 RESET

In addition to the conditions given in the

“PCD33xxA

Family” data sheet, all derivative registers are cleared in

the reset state.

11 IDLE MODE

In Idle mode, the frequency generator, the EEPROM and

the Timer 2 sections remain operative. Therefore, the

IDLE instruction may be executed while an erase and/or

write access to EEPROM is in progress.

12 STOP MODE

Since the oscillator is switched off, the frequency

generator, the EEPROM and the Timer 2 sections receive

no clock. It is suggested to clear both the HGF and the

LGF registers before entering Stop mode. This will cut off

the biasing of the internal amplifiers, considerably

reducing current requirements.

The Stop mode must not be entered while an erase

and/or write access to EEPROM is in progress. The STOP

instruction may only be executed when EWP in EPCR is

zero. The Timer 2 section is frozen during Stop mode.

After exit from Stop mode by a HIGH level on CE/T0,

Timer 2 proceeds from the held state.

13 INSTRUCTION SET RESTRICTIONS

As RAM space is restricted to 128 bytes, care should be

taken to avoid accesses to non-existing RAM locations.

14 OVERVIEW OF PORT AND POWER-ON-RESET CONFIGURATION

Table 24 Port and Power-on-reset conﬁguration

See note 1 and 2.

Notes

1. Port output drive: 1 = standard I/O; 2 = open-drain I/O, see

“PCD33xxA Family” data sheet.

2. Port state after reset: S = Set (HIGH) and R = Reset (LOW).

3. The Melody Output drive type is push-pull.

TYPE

PORT 0

PORT 1

PORT 2

VPOR

01234567012345

0123

PCD3755A

1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R(3)

1.3 V

PCD3755E

1S 1S 1S 1S 1S 1S 1S 1S 2S 2S 2S 2S 2S 2S 1S 1S(3)

2.0 V

PCD3755F

1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1S 1R 1R(3)

2.0 V

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