EEPROM

EEPROM

EEPROM

EEPROM

EEPROM

AS58C1001

Austin Semiconductor, Inc.

AS58C1001

Rev. 5.0 7/02

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

End

Of

Life

For more products and information

please visit our web site at

www.austinsemiconductor.com

128K x 8 EEPROM

EEPROM Memory

AVAILABLE AS MILITARY

SPECIFICATIONS

!

SMD 5962-38267

!

MIL-STD-883

FEATURES

!

High speed: 150, 200, and 250ns

!

Data Retention: 10 Years

!

Low power dissipation, active current (20mW/MHz (TYP)),

standby current (100

µW(MAX))

!

Single +5V (+10%) power supply

!

Data Polling and Ready/Busy Signals

!

Erase/Write Endurance (10,000 cycles in a page mode)

!

Software Data protection Algorithm

!

Data Protection Circuitry during power on/off

!

Hardware Data Protection with RES pin

!

Automatic Programming:

Automatic Page Write: 10ms (MAX)

128 Byte page size

OPTIONS

MARKINGS

!

Timing

150ns access

-15

200ns access

-20

250ns access

-25

!

Packages

Ceramic LCC

ECA No. 208

Ceramic Flat Pack

F

No. 306

Radiation Shielded Ceramic FP* SF

No. 305

Ceramic SOJ

DCJ No. 508

Plastic SOP

DG

!

Operating Temperature Ranges

XT

IT

*NOTE: Package lid is connected to ground (Vss).

32-Pin LCC (ECA)

GENERAL DESCRIPTION

The Austin Semiconductor, Inc. AS58C1001 is a 1 Megabit CMOS

Electrically Erasable Programmable Read Only Memory (EEPROM)

organized as 131, 072 x 8 bits. The AS58C1001 is capable or in

system electrical Byte and Page reprogrammability.

The AS58C1001 achieves high speed access, low power

consumption, and a high level of reliability by employing advanced

MNOS memory technology and CMOS process and circuitry

technology and CMOS process and circuitry technology.

This device has a 128-Byte Page Programming function to make its

erase and write operations faster. The AS58C1001 features Data

Polling and a Ready/Busy signal to indicate completion of erase and

programming operations.

This EEPROM provides several levels of data protection.

Hardware data protection is provided with the RES pin, in addition to

noise protection on the WE signal and write inhibit during power on

and off. Software data protection is implemented using JEDEC

Optional Standard algorithm.

The AS58C1001 is designed for high reliability in the most

demanding applications. Data retention is specified for 10 years and

erase/write endurance is guaranteed to a minimum of 10,000 cycles in

the Page Mode.

PIN ASSIGNMENT

(Top View)

32-Pin CFP (F & SF), 32-Pin CSOJ (DCJ),

32-Pin SOP (DG)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

RDY/BUSY\

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O 0

I/O 1

I/O 2

Vss

Vcc

A15

RES\

WE\

A13

A8

A9

A11

OE\

A10

CE\

I/O 7

I/O 6

I/O 5

I/O 4

I/O 3

4

3 2 1 32 31 30

14 15 16 17 18 19 20

5

6

7

8

9

10

11

12

13

29

28

27

26

25

24

23

22

21

A7

A6

A5

A4

A3

A2

A1

A0

I/O 0

A14

A13

A8

A9

A11

OE\

A10

CE\

I/O 7