VT6306 datasheet(21/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-15-

PHY Registers

Table 3. PHY Register Map

Offset

0000b

Physical ID

0001b

Gap Count

IBR

RHB

0010b

Total Ports

always 111b

0011b

Delay

Max Speed

0100b

Power Class

Jitter

Cont

0101b Multi Accel

Tout

Loop ISBR

0110b

-reserved-

0111b

Port Select

Page Select

1000b

1001b

1010b

1011b

1100b

1101b

1110b

1111b

Physical ID = Address of This Node

R = Root Node

PS = Cable Power Status

RHB = Root Hold-Off

IBR = Initiate Bus Reset

Gap Count = For Gap Time Optimization

Total Ports = 3

Max Speed = Supports 98.304, 196.608, & 393.216 Mbit/s

Delay = Worst Case Repeater Delay

LC = Link Control

Cont = Contender

Jitter = Repeater Delay Variation

WT = Watchdog Timer Enable

ISBR = Initiate Short (Arbitrated) Bus Reset

Loop = Loop Detect

PF = Cable Power Fail Detect

Tout = Arbitration State Machine Timeout

PE = Port Event Detect

Accel = Arbitration Acceleration Enable

Multi = Multispeed Packet Concatenation Enable

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