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PCD5091 数据表(PDF) 8 Page - NXP Semiconductors

部件名 PCD5091
功能描述  DECT baseband controller
PDF  16 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCD5091 数据表(HTML) 8 Page - NXP Semiconductors

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1997 Jul 21
8
Philips Semiconductors
Objective specification
DECT baseband controller
PCD5091
DCK
27
25
I/O
input
ISF2DPES
ISF2UPES
ADPCM output or IOM data clock
input/output (ISF2UPES in PCD5090/xxx,
PCA5097/xxx)
DI
28
26
I
−
DIPP0PES
ADPCM or IOM data input
FS1
29
27
I/O
input
ISF2DPES
ISF2UPES
8 kHz framing input/output
(ISF2UPES in PCD5090/xxx, PCA5097/xxx)
DO
30
28
O
off
ISI8DPES
ADPCM or IOM data output
XTAL2
31
29
O
running
ANAIOD1
crystal oscillator output
XTAL1
32
30
I
−
ANAIOD1
crystal oscillator input
VANLO
33
31
O
1.0 V
ANAIOD1
analog output from D/A converter
VSSO
34
32
−−
supply
negative supply voltage for the oscillator
VDDO
35
33
−−
supply
positive supply voltage for the oscillator
LIFM
36
34
I
0.7 V
ANAIOD1
negative input from line interface
LIFP
37
35
I
0.7 V
ANAIOD1
positive input from line interface
VSSA
38
36
−−
supply
negative supply voltage for analog circuits
MICM
39
37
I
0.7 V
ANAIOR1
negative input from microphone
MICP
40
38
I
0.7 V
ANAIOR1
positive input from microphone
VMIC
41
39
O
off
ANAIOD1
positive microphone supply voltage (+2 V)
Vref
42
40
O
2.0 V
ANAIOD1
reference voltage (+2 V)
VBGP
43
41
O
1.25 V
ANAIOR1
bandgap output voltage (+1.25 V)
VDDA
44
42
−−
supply
positive supply voltage for analog circuits
EARM
45
43
O
1.4 V
ANAIOD1
negative output to earpiece
EARP
46
44
O
1.4 V
ANAIOD1
positive output to earpiece
EN_WATCHDOG
47
45
I
−
DIUP0PES
watchdog enable input
P1.0
48
46
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.1
49
47
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.2
50
48
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
GP_CLK7
51
49
O
L
ISP2DPES
general purpose 6.912 MHz output
DPLL_DATA
52
50
O
L
ISP2DPES
data after clock recovery network
R_SLICED
53
51
O
L
ISP2DPES
R_DATA comparator output
VDD5V_1
54
52
−−
supply
positive supply voltage 1 for the +5 V
interface
P1.3
55
53
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
P1.4
56
54
I/O
H
ISQ2CPES
bidirectional 80C51 port pin
SYMBOL
PIN
I/O
STATE
AFTER
RESET
PIN TYPE
PIN DESCRIPTION
QFP100 LQFP100



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