©NEC Electronics Corporation 2004

78K0/KF2

ZUD-CC-04-0129-E

Data Published Oct 2004 N CP(K)

(f) 3-wire serial I/O mode with automatic transmit/ receive function (AUTOCSI

SCKA0

…internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.0 V

≤ VDD ≤ 5.5 V

600

ns

SCKA0 cycle time

tKCY3

2.7 V

≤ VDD < 4.0 V

1200

ns

4.0 V

≤ VDD ≤ 5.5 V

tKCY3/2 - 50

Not1

ns

SCKA0 high-/low-level width

tKH3

tKL3

2.7 V

≤ VDD < 4.0 V

tKCY3/2 - 100

Not1

ns

SIA0 setup time (to SCKA0

↑)tSIK3

100

ns

SIA0 hold time (to SCKA0

↑)

tKSI3

300

ns

4.0 V

≤ VDD ≤ 5.5 V

200

ns

Delay time from SCKA0

↓ to

SOA0

tKSO3

C = 100 pF

Note2

2.7 V

≤ VDD < 4.0 V

300

ns

Time from SCKA0

↑ to STB0↑

tSBD

tKCY3/2 - 100

Not1

ns

4.0 V

≤ VDD ≤ 5.5 V

tKCY3 - 30

Not1

ns

Strobe signal high level width

tSBW

2.7 V

≤ VDD < 4.0 V

tKCY3 - 60

Not1

ns

Busy signal setup time (to

busy signal detection timing)

tBYS

100

ns

4.0 V

≤ VDD ≤ 5.5 V

100

ns

Busy signal hold time (from

busy signal detection timing)

tBYH

2.7 V

≤ VDD < 4.0 V

150

ns

Time from busy inactive to

SCKA0

↓

tSPS

2tKCY3

ns

Notes 1. This is the value when the high-speed system clock (fXH) is operating.

2.

C is the load capacitance of the SCKA0 and SOA0 output lines.

(g) 3-wire serial I/O mode with automatic transmit/ receive function (AUTOCSI

SCKA0

…external clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.0 V

≤ VDD ≤ 5.5 V

600

ns

SCKA0 cycle time

tKCY4

2.7 V

≤ VDD < 4.0 V

1200

ns

4.0 V

≤ VDD ≤ 5.5 V

T.B.D

ns

SCKA0 high-/low-level width

tKH4

tKL4

2.7 V

≤ VDD < 4.0 V

T.B.D

ns

SIA0 setup time (to SCKA0

↑)tSIK4

100

ns

SIA0 hold time (to SCKA0

↑)

tKSI4

300

ns

4.0 V

≤ VDD ≤ 5.5 V

200

ns

Delay time from SCKA0

↓ to

SOA0 output

tKSO4

C = 50 pF

Note

2.7 V

≤ VDD < 4.0 V

300

ns

Note

C is the load capacitance of the SOA0 output lines.

Caution

Specification at 1.8 V ≤ VDD < 2.7V is not fixed.