PCF2116 datasheet(8/64 Pages) PHILIPS

8 / 64 page

1997 Apr 07

Philips Semiconductors

Product speciﬁcation

LCD controller/drivers

PCF2116 family

8.2

LCD supply voltage generator, PCF2116K

In the PCF2116K version, V0 is connected through an

on-chip resistor (R0) to VLCD. Resistor R0 has a nominal

value of 1 M

Ω and draws a typical current of 4 µA from the

pin V0. A constant voltage (equal to 1.34VDD) is always

present across R0.

The voltage range of the PCF2116K is between VSS and

VDD − 0.5 V (see Fig.4). When V0 is connected to VDD the

generator is switched off and an external voltage must be

supplied to pin VLCD. This may be more negative than VSS.

When G = logic 1 the generator produces a negative

voltage at pin VLCD, controlled by the input voltage at

pin V0. The LCD operating voltage is given by the

relationship:

VOP = 2.34VDD − V0

Where:

VOP =VDD − VLCD

VLCD =V0 − (1.34VDD)

When G = logic 0, the generated output voltage VLCD is

equal to V0 (between VSS and VDD). In this instance:

VOP =VDD − V0

8.3

Character generator ROM (CGROM)

The standard character sets A, C and G are available for

the PCF2114x and PCF2116x. Standard character set C is

available for the PCF2116K.

8.4

LCD bias voltage generator

The intermediate bias voltages for the LCD display are

also generated on-chip. This removes the need for an

external resistive bias chain and significantly reduces the

system power consumption. The optimum levels depend

on the multiplex rate and are selected automatically when

the number of lines in the display is defined.

The optimum value of VOP depends on the multiplex rate,

the LCD threshold voltage (Vth) and the number of bias

levels and is given by the relationships in Table 1.Using a

5-level bias scheme for 1 : 16 MUX rate allows VOP <5V

for most LCD liquids. The effect on the display contrast is

negligible.

8.5

Oscillator

The on-chip oscillator provides the clock signal for the

display system. No external components are required.

Pin OSC must be connected to VDD.

8.6

External clock

If an external clock is to be used, it must be input at

pin OSC. The resulting display frame frequency is given by

fframe = 1⁄2304fosc . A clock signal must always be present,

otherwise the LCD may be frozen in a DC state.

8.7

Power-on reset

The power-on reset block initializes the chip after

power-on or power failure.

8.8

Registers

The PCF2116 has two 8-bit registers, an Instruction

Select signal (RS) determines which register will be

accessed.

The instruction register stores instruction codes such as

‘Display clear’ and ‘Cursor shift’, and address information

for the Display Data RAM (DDRAM) and Character

Generator RAM (CGRAM). The instruction register can be

written to, but not read, by the system controller.

The data register temporarily stores data to be read from

the DDRAM and CGRAM. When reading, data from the

DDRAM or CGRAM corresponding to the address in the

Address Counter is written to the data register prior to

being read by the ‘Read data’ instruction.

8.9

Busy Flag

The Busy Flag indicates the free/busy status of the

PCF2116. Logic 1 indicates that the chip is busy and

further instructions will not be accepted. The Busy Flag is

output to pin DB7 when RS = logic 0 and R/W = logic 1.

Instructions should only be written after checking that the

Busy Flag is logic 0 or waiting for the required number of

clock cycles.

Table 1

Optimum values for VOP

MUX RATE

NUMBER OF BIAS

LEVELS

VOP/Vth

DISCRIMINATION

Von/Voff

1 : 16

3.67

1.277

1 : 32

5.19

1.196

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