PCF2131 datasheet(49/85 Pages) NXP

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NXP Semiconductors

PCF2131

Nano-power highly accurate RTC with integrated quartz crystal

prescaler can be set into a known state by using bit STOP and CPR. When bit STOP and CPR are logic 1, the

prescaler is reset to 0. STOP and CPR must be cleared before the prescaler can operate again.

From a stop condition, the first 1 second increment will take place after 8192 positive edges on pin CLKOUT.

Thereafter, every 8192 positive edges cause a 1 second increment. In 100 Hz mode, the first 100th of a second

increment will take place after 80 pulses on pin CLKOUT, and the first 1 second increment will take place after

8176 pulses on pin CLKOUT. Thereafter, every 8192 pulses cause a 1 second increment. The 100 Hz clock

is generated from a dithered state machine which runs on the 256 Hz clock, so the number of pulses for each

subsequent 100ths change is not constant. After the first 1 second increment the 25-bit dither pattern proceeds

as follows from left to right: 1101010101101010110101010

Where 1 == 96 CLKOUT pulses, and 0 == 64 CLKOUT pulses. This pattern repeats 4 times every second.In

the first second, after 80 clock pulses trigger the first 100th,the left pattern is 101010101101010110101010,

1101010101101010110101010, 1101010101101010110101010, 1101010101101010110101010, which means

96 pulses for 100ths == 2, then 64 pulses for 100ths == 3, 96 for 100ths == 4, and so on.

Remark: Entry into test mode is not synchronized to the internal 8192 Hz clock. When entering the test mode,

no assumption as to the state of the prescaler can be made.

Operating example:

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111).

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

6. Clear STOP (register Control_1, STOP is logic 0).

7. Apply 8192 clock pulses to CLKOUT.

8. Read time registers to see the first change.

9. Apply 8192 clock pulses to CLKOUT.

10. Read time registers to see the second change.

Repeat 7 and 8 for additional increments.

Operating example (100 Hz mode):

1. Set CLKOUT = high-Z (register CLKOUT_ctl, COF[2:0] = 111.

2. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1).

3. Set bit STOP (register Control_1, STOP is logic 1).

4. Set bit CPR (register SR_RESET, CPR is logic 1).

5. Set time registers to desired value.

6. Clear STOP (register Control_1, STOP is logic 0).

7. Apply 80 clock pulses to CLKOUT.

8. Read hundredths registers to see the first change.

9. Apply 8096 clock pulses to CLKOUT (8096 + 80 = 8176 total pulses).

10. Read seconds registers to see the first change.

11. Apply the number of pulses needed for the current dither value.

12. Read the hundredths register to see subsequent changes.

13. Read the seconds register every 8192 pulses to see subsequent changes.

7.15 STOP bit function

The STOP bit stops the time from counting in both RTC mode and external clock test mode. STOP must be set

to unlock the time and date registers to set the time.

PCF2131

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.0 — 5 October 2023

49 / 85

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