PCF5083 datasheet(9/136 Pages) PHILIPS

9 / 136 page

1996 Oct 29

Philips Semiconductors

Objective speciﬁcation

GSM signal processing IC

PCF5083

GPON1

Sleep mode power-down 1 (active HIGH, 3-state).

GPON2

Sleep mode power-down 2 (active HIGH, open-drain output).

REFON

Sleep mode power-down 3 (active HIGH, 3-state).

DCLK

External DSP clock input.

RSTP

PLL reset (active LOW with internal pull-down resistor).

CLKSEL

Timer clock source select.

VSSPLL

Ground for PLL.

CKO

Low swing input buffer output.

VSS1

Ground I/O pin.

VDD1

Supply I/O pin.

CKI

Reference clock input, low swing input 13 kHz.

VDDPLL

Supply for PLL.

TMS

JTAG port mode select (with internal pull-down resistor).

TDI

JTAG port data input (with internal pull-down resistor).

TDO

JTAG port data output.

TCKIO

Auxiliary test signal - tied to VSS during operation.

TRSTN

JTAG port reset (with internal pull-down resistor).

VDD2

Supply core.

VSS2

Ground core.

TCK

JTAG port clock input (with internal pull-down resistor).

HCEN_T

Host Interface Enable - Timer core (active LOW).

IO1/AEN

I/O

DSP general purpose I/O used for voice port control (CMOS level I/O). The

PCF5083-3 has its own internal pull-up resistor however, both the PCF5083-2B

and PCF5083-2C require a pull-up resistor.

IO2

I/O

DSP general purpose I/O used for voice port control (CMOS level I/O). The

PCF5083-3 has its own internal pull-up resistor however, both the PCF5083-2B

and PCF5083-2C require a pull-up resistor.

IO3/IRQN2

I/O

DSP general purpose I/O or Interrupt Request Input 2 (CMOS level I/O). The

PCF5083-3 has its own internal pull-up resistor however, both the PCF5083-2B

and PCF5083-2C require a pull-up resistor.

IO4/DTX

I/O

DSP general purpose I/O (CMOS level I/O, external pull-up resistor required).

HA0 to HA6

88 to 94

Host Interface Address.

HD0 to HD3

95 to 98

I/O

Host Interface Data (3-state).

SYMBOL

I/O

DESCRIPTION

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PCF5083 数据表(PDF) 9 Page - NXP Semiconductors

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