PCF8548 datasheet(13/40 Pages) PHILIPS

13 / 40 page

1999 Aug 16

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8548

11 I2C-BUS INTERFACE

11.1

Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication

between different ICs or modules. The two lines are a

Serial Data line (SDA) and a Serial Clock line (SCL). Both

lines must be connected to a positive supply via a pull-up

resistor. Data transfer may be initiated only when the bus

is not busy.

11.1.1

BIT TRANSFER

One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the

HIGH period of the clock pulse because changes in the

data line at this time will be interpreted as a control signal.

Bit transfer is illustrated in Fig.10.

11.1.2

START AND STOP CONDITIONS

Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the

clock is HIGH is defined as the START condition (S).

A LOW-to-HIGH transition of the data line while the clock

is HIGH is defined as the STOP condition (P). The START

and STOP conditions are illustrated in Fig.11.

11.1.3

SYSTEM CONFIGURATION

The system configuration is illustrated in Fig.12.

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from the

bus

• Master: the device which initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-Master: more than one master can attempt to

control the bus at the same time without corrupting the

message

• Arbitration: procedure to ensure that, if more than one

master simultaneously tries to control the bus, only one

is allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clock

signals of two or more devices.

11.1.4

ACKNOWLEDGE

Each byte of eight bits is followed by an acknowledge bit.

The acknowledge bit is a HIGH signal put on the bus by the

transmitter during which time the master generates an

extra acknowledge related clock pulse. A slave receiver

which is addressed must generate an acknowledge after

the reception of each byte. A master receiver must also

generate an acknowledge after the reception of each byte

that has been clocked out of the slave transmitter.

The device that acknowledges must pull-down the SDA

line during the acknowledge clock pulse, so that the SDA

line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times

must be taken into consideration). A master receiver must

signal an end-of-data to the transmitter by not generating

an acknowledge on the last byte that has been clocked out

of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a STOP

condition. Acknowledgement on the I2C-bus is illustrated

in Fig.13.

Fig.10 Bit transfer.

handbook, full pagewidth

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

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