PCF8549USLASH2 datasheet(13/36 Pages) PHILIPS

13 / 36 page

1997 Nov 21

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8549

I2C-bus protocol

The PCF8549 supports both read and write access. The

R/W bit is part of the slave address.

Before any data is transmitted on the I2C-bus, the device

which should respond is addressed first. Two 7-bit slave

addresses (0111100 and 0111101) are reserved for the

PCF8549. The least significant bit of the slave address is

set by connecting the input SA0 to either logic 0 (VSS1) or

1(VDD1).

The I2C-bus protocol is illustrated in Fig.13.

The sequence is initiated with a START condition (S) from

the I2C-bus master which is followed by the slave address.

All slaves with the corresponding address acknowledge in

parallel, all the others will ignore the I2C-bus transfer. After

acknowledgement, one or more command words follow

which define the status of the addressed slaves. A

command word consists of a control byte, which defines

Co and D/C, plus a data byte (see Fig.13 and Table 1).

The last control byte is tagged with a cleared most

significant bit, the continuation bit Co. After a control byte

with a cleared Co-bit, only data bytes will follow. The state

of the D/C-bit defines whether the data-byte is interpreted

as a command or as RAM-data.The control and data bytes

are also acknowledged by all addressed slaves on the bus.

After the last control byte, depending on the D/C bit

setting, either a series of display data bytes or command

data bytes may follow. If the D/C bit was set to ‘1’, these

display bytes are stored in the display RAM at the address

specified by the data pointer. The data pointer is

automatically updated and the data is directed to the

intended PCF8549 device. If the D/C bit of the last control

byte was set to ‘0’, these command bytes will be decoded

and the setting of the device will be changed according to

the received commands. The acknowledgement after

each byte is made only by the addressed slave. At the end

of the transmission the I2C-bus master issues a stop

condition (P).

If the R/W bit is set to one in the slave-address, the chip

will output data immediately after the slave-address

according to the D/C bit, which was sent during the last

write access. If no acknowledge is generated by the

master after a byte, the driver stops transferring data to the

master.

Fig.13 I2C-bus protocol.

control byte

data byte

control byte

data byte

11 1

slave address

2n > 0 bytes

1 byte

n > 0 bytes

MSB................. LSB

PCF8549

slave address

acknowledgement

from PCF8549

11 1

acknowledgement

from PCF8549

acknowledgement

from PCF8549

acknowledgement

from PCF8549

acknowledgement

from PCF8549

data byte

slave address

acknowledgement

from Master

11 1

acknowledgement

from Master

acknowledgement

from Master

acknowledgement

from Master

data byte

CO DC 0 0 0 000 A

Control Byte

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