Philips Semiconductors

PCF8563

Real-time clock/calendar

Product specification

16 April 1999

14 of 30

9397 750 04855

© Philips Electronics N.V. 1999. All rights reserved.

8.9.3

Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time will be interpreted as a control signal; see Figure 8.

8.9.4

Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an

acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the

transmitter during which time the master generates an extra acknowledge related

clock pulse.

A slave receiver which is addressed must generate an acknowledge after the

reception of each byte. Also a master receiver must generate an acknowledge after

the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Fig 8.

dth

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 9.

width

MBC602

S

START

condition

9

8

2

1

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER