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PCF8573P 数据表(PDF) 9 Page - NXP Semiconductors |
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PCF8573P 数据表(HTML) 9 Page - NXP Semiconductors |
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9 / 24 page ![]() 1997 Mar 28 9 Philips Semiconductors Product specification Clock/calendar with Power Fail Detector PCF8573 9I2C-BUS PROTOCOL 9.1 Addressing Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. The clock/calendar acts as a slave receiver or slave transmitter. Therefore the clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line. The clock/calendar slave address is shown in Fig.7. Bits A0 and A1 correspond to the two hardware address pins A0 and A1. Connecting these to VDD or VSS allows the device to have 1 of 4 different addresses. 9.2 Clock/calendar READ/WRITE cycles The I2C-bus configuration for different clock/calendar READ and WRITE cycles is shown in Figs 8, 9 and 10. The write cycle is used to set the time counter, the alarm register and the flags. The transmission of the clock/calendar address is followed by the MODE-POINTER-word which contains a CONTROL-nibble (Table 3) and an ADDRESS-nibble (Table 4). The ADDRESS-nibble is valid only if the preceding CONTROL-nibble is set to EXECUTE ADDRESS. The third transmitted word contains the data to be written into the time counter or alarm register. Fig.7 Slave address. Fig.8 Master transmitter transmits to clock/calendar slave receiver. |
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