PCF8812USLASH2 datasheet(10/36 Pages) PHILIPS

10 / 36 page

2000 Nov 22

Philips Semiconductors

Product speciﬁcation

× 102 pixels matrix LCD driver

PCF8812

handbook, full pagewidth

MGS396

012

102

103

104

204

205

206

306

307

308

408

409

410

510

511

512

612

613

614

714

715

716

816

817

818

917

101

X address

Y address

Fig.6 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

10 INSTRUCTIONS

The instruction format is divided into two modes: If D/C

(mode select) is set LOW the current byte is interpreted as

command byte (see Table 1). Figure 8 shows an example

of a serial data stream for initializing the chip. If D/C is set

HIGH the following bytes are stored in the display data

RAM. After every data byte the address counter is

incremented automatically. The level of the D/C signal is

read during the last bit of the data byte. Every instruction

can be sent in any order to the PCF8812. The MSB of a

byte is transmitted first. Figure 8 shows one possible

command stream, used to set-up the LCD driver. The

serial interface is initialized when SCE is HIGH. In this

state SCLK clock pulses have no effect and no power is

consumed by the serial interface. A negative edge on SCE

enables the serial interface and indicates the start of a data

transmission.

Figures 9 and 10 show the serial bus protocol:

• When SCE is HIGH, SCLK clocks are ignored. During

the HIGH time of SCE the serial interface is initialized

(see Fig.12)

• SDIN is sampled at the positive edge of SCLK

• D/C indicates whether the byte is a command (D/C=0)

or RAM data (D/C = 1). It is read with the eighth SCLK

pulse

• If SCE stays LOW after the last bit of a command/data

byte, the serial interface expects DB7 of the next byte at

the next positive edge of SCLK (see Fig.12). If SCLK

goes LOW after the last data bit (DB0), either:

– A rising clock edge is required to latch the last data bit

– Or the last bit is latched when SCE goes HIGH.

• A reset pulse with RES interrupts the transmission.

No data is written into the RAM. The registers are

cleared. If SCE is LOW after the positive edge of RES,

the serial interface is ready to receive bit 7 of a

command/data byte (see Fig.12).

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