Philips Semiconductors

Product specification

PCK2000

CK97 (66/100MHz) System Clock Generator

1998 Sep 29

8

AC CHARACTERISTICS

VDDREF = VDDPCI (0–1) = VDD48MHz = 3.3V

CPU CLOCK OUTPUTS, CPU(0–3) (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

CPUCLK period

2

15.0

15.5

CPUCLK HIGH time

66MHz

1, 5

5.2

ns

CPUCLK LOW time

1, 5

5.0

CPUCLK period

2

10.0

10.5

CPUCLK HIGH time

100MHz

1, 5

3.0

ns

CPUCLK LOW time

1, 5

2.8

CPUCLK rise time

9

0.4

1.6

ns

CPUCLK fall time

9

0.4

1.6

ns

CPUCLK jitter

175

ps

Output Duty Cycle

1

45

55

%

CPU Bus CLK skew

2

175

ps

CPUCLK stabilization from Power-up

7

3

ms

PCI CLOCK OUTPUTS, PCI(0–7) (LUMP CAPACITANCE TEST LOAD = 30pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

PCICLK period

3

30.0

ns

PCICLK period stability

8

500

ps

PCICLK HIGH time

1

12.0

ns

PCICLK LOW time

1

12.0

ns

PCICLK rise time

10

0.5

2.0

ns

PCICLK fall time

10

0.5

2.0

ns

PCI Bus CLK skew

2

500

ps

CPUCLK to PCICLK Offset

2, 4

1.5

4.0

ns

PCICLK stabilization from Power-up

7

3

ms

APIC(0–1) CLOCK OUTPUT (LUMP CAPACITANCE TEST LOAD = 20pF)

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

f

Frequency, Actual

Frequency generated

by Crystal

14.31818

MHz

Output rise edge rate

1

4

ns

Output fall edge rate

1

4

ns

Duty Cycle

45

55

%

Frequency stabilization from Power-up (cold start)

3

ms