Philips Semiconductors

Product data

PCK2002M

2001 Jul 19

5

AC CHARACTERISTICS

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

NOTES

MIN

MAX

SDRAM rise time

2, 4

1.5

2.0

4.0

V/ns

SDRAM fall time

2, 4

1.5

2.9

4.0

V/ns

SDRAM buffer LH propagation delay

4, 5

1.2

2.7

3.5

ns

SDRAM buffer HL propagation delay

4, 5

1.2

2.7

3.5

ns

SDRAM buffer enable time

4, 5

1.0

2.6

5.0

ns

SDRAM buffer disable time

4, 5

1.0

2.7

5.0

ns

DUTY CYCLE

Output Duty Cycle

Measured at 1.5 V

3, 4, 5

45

52

55

%

SDRAM Bus CLK skew

1, 4

—

150

250

ps

Device to device skew

—

—

500

ps

NOTES:

1. Skew is measured on the rising edge at 1.5 V.

3. Duty cycle should be tested with a 50/50% input.

4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.

5. Input edge rate for these tests must be faster than 1 V/ns.

6. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to

ensure duty cycle specification is met.

8. Typical is measured with MAX (30 pF) discrete load.

9. Typical is measured with MIN (20 pF) discrete load.