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AM62A7 数据表(PDF) 171 Page - Texas Instruments |
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AM62A7 数据表(HTML) 171 Page - Texas Instruments |
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171 / 238 page  Table 7-80 presents timing conditions for MMC0. Table 7-80. MMC0 Timing Conditions PARAMETER MIN MAX UNIT INPUT CONDITIONS SRI Input slew rate Legacy SDR @ 3.3 V High Speed SDR@ 3.3V Default Speed High Speed 0.69 2.06 V/ns Legacy SDR @ 1.8 V UHS-I SDR12 0.14 1.44 V/ns High Speed SDR @ 1.8 V UHS-I SDR25 0.3 1.34 V/ns UHS-I DDR50 1 2 V/ns OUTPUT CONDITIONS CL Output load capacitance HS200 UHS-I SDR104 1 10 pF All other modes 1 12 pF PCB CONNECTIVITY REQUIREMENTS td(Trace Delay) Propagation delay of each trace Legacy SDR High Speed SDR HS200 126 756 ps Default Speed High Speed UHS-I SDR12 UHS-I SDR25 UHS-I SDR50 UHS-I SDR104 126 1386 ps UHS-I DDR50 239 1134 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces High Speed SDR HS200 High Speed UHS-I SDR104 8 ps UHS-I DDR50 20 ps All other modes 100 ps www.ti.com AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 171 Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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