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AM62A7 数据表(PDF) 183 Page - Texas Instruments |
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AM62A7 数据表(HTML) 183 Page - Texas Instruments |
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183 / 238 page ![]() Table 7-98 presents timing conditions for MMC1. Table 7-98. MMC1/MMC2 Timing Conditions PARAMETER MIN MAX UNIT Input Conditions SRI Input slew rate Default Speed High Speed 0.69 2.06 V/ns UHS–I SDR12 UHS–I SDR25 0.34 1.34 V/ns UHS–I DDR50 1 2 V/ns Output Conditions CL Output load capacitance All modes 1 10 pF PCB Connectivity Requirements td(Trace Delay) Propagation delay of each trace UHS–I DDR50 239 1134 ps All other modes 126 1386 ps td(Trace Mismatch Delay) Propagation delay mismatch across all traces High Speed UHS–I SDR104 8 ps UHS–I DDR50 20 ps All other modes 100 ps www.ti.com AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 183 Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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