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AM62A7 数据表(PDF) 126 Page - Texas Instruments |
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AM62A7 数据表(HTML) 126 Page - Texas Instruments |
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126 / 238 page ![]() 7.10.5.4 DDRSS For more details about features and additional description information on the device LPDDR4 Memory Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Table 7-41 and Figure 7-34 present switching characteristics for DDRSS. Table 7-41. DDRSS Switching Characteristics see Figure 7-34 NO. PARAMETER DDR TYPE MIN MAX UNIT 1 tc(DDR_CKP/ DDR_CKN) Cycle time, DDR_CKP and DDR_CKN LPDDR4 0.5358(1) 20 ns (1) Minimum DDR clock Cycle time will be limited based on the specific memory type (vendor) used in a system and by PCB implementation. Refer to AM62Ax DDR Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. DDR0_CKP 1 DDR0_CKN Figure 7-34. DDRSS Switching Characteristics For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM. AM62A7, AM62A7-Q1, AM62A3, AM62A3-Q1 SPRSP77A – MARCH 2023 – REVISED AUGUST 2023 www.ti.com 126 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: AM62A7 AM62A7-Q1 AM62A3 AM62A3-Q1 |
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