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AS7341L

Datasheet

• PUBLIC

DS000718

• v1-00 • 2020-May-25

│ 43

STATUS Register (Address 0x93)

The primary status register for AS7341L indicates if there are saturation or interrupt events that need

to be handled by the user. This register is self-

clearing, meaning that writing a “1” to any bit in the

indicated event(s) and then write the register value back to STATUS to clear the handled events.

Writing “0” will not clear those bits if they have a value of “1”, which means that new events that

occurred since the last read of the STATUS register will not be accidentally cleared.

Figure 60:

STATUS Register

Addr: 0x93

STATUS

Bit

Bit Name

Default

Access

Bit Description

7:4

reserved

AINT

R, SC

Spectral Channel Interrupt.

If SP_IEN is set, indicates that a spectral event that

met the programmed thresholds and persistence

(APERS) occurred.

FINT

R, SC

FIFO Buffer Interrupt.

If FIEN is set, indicates that the FIFO_LVL fulfills the

threshold condition. If cleared by writing 1, the

interrupt will be asserted again as more data is

collected. To fully clear this interrupt, all data must

be read from the FIFO buffer.

CINT

R, SC

Calibration Interrupt.

SINT

R, SC

System Interrupt.

If SIEN is set, indicates that system interrupt is set.

Refer to Figure 63 Status 5 register.

STATUS 2 Register (Address 0xA3)

Figure 61:

STATUS 2 Register

Addr: 0xA3

STATUS 2

Bit

Bit Name

Default

Access

Bit Description

reserved

AVALID

Spectral Valid.

Indicates that the spectral measurement has been

completed

reserved

ASAT_DIGITAL

Digital Saturation.

Indicates that the maximum counter value has been

reached. Maximum counter value depends on

integration time set in the ATIME register.

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