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AS8579

Functional Description

Datasheet

• PUBLIC

DS000707

• v4-01 • 2022-Jun-08

│ 18

6.2

SPI Interface

The sensor contains a single serial peripheral interface (SPI), consisting of Serial Clock (SCLK), Data

Out (MISO), Data In (MOSI), and Chip Select (CS) pins. The AS8579 is configured as a SPI slave.

The SPI interface is used to edit Register content, access Control and readout Sensor Values

The CS input selects this device for serial transfers. CS is active high. Register data is shifted in the

MOSI pin and shifted out the MISO pin on each subsequent SCLK. The CS input has a pull-down

internal to the IC, which pulls this pin to the negated state should an open circuit condition occur.

The SCLK input is the clock signal input for synchronization of serial data transfer. When CS is

asserted, both the SPI master and the slave latch input data on the rising edge of SCLK. The SPI

master typically shifts data out on the falling edge of SCLK, as does this device. SCLK input has a

pull-down internal to the AS8579 which pulls this pin to the negated state should an open circuit

condition occur. SCLK can idle in either state (high or low).

The MISO output pin is in a tri-state condition when CS is low. Data is transmitted on MISO MSB first.

MISO has a weak pull-down to set the bus to a defined state when the output is in tri-state mode.

MOSI takes data from the master microprocessor while CS is asserted. Data is received MSB first.

MOSI has a pull-down internal to the AS8579 which pulls this pin to the negated state should an open

circuit condition occur.

Figure 13:

SPI TIMING

Symbol

Parameter

Min

Typ

Max

Unit

tSCK

SCLK Period

125

tLEAD

Enable Lead Time

16.25

tLAG

Enable Lag Time

12.5

tSCKHS

SCLK High Time

tSCKLS

SCLK Low Time

tSUS

MOSI Input Setup Time

tHS

MOSI Input Hold Time

MISO Access Time

tDIS

MISO Disable Time

tVS

MISO Output Valid Time

tHO

MISO Output Hold Time

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