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AS8579-ASST 数据表(PDF) 33 Page - OSRAM GmbH |
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AS8579-ASST 数据表(HTML) 33 Page - OSRAM GmbH |
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33 / 44 page ![]() Document Feedback AS8579 Register Description Datasheet • PUBLIC DS000707 • v4-01 • 2022-Jun-08 43 │ 32 Current Buffer Gain Program Parameter Min Typ Max Unit CBG=3 11 2.02 2.25 2.47 kOhm 7.2.12 Demodulation Clock Selection (Address 0x26/0x36) In this register, you can set the demodulation clock frequency for I and Q-path Figure 36: DCLK Settings DCLK Value Program Parameter Upper Path Lower Path Signal Clock Clock Phase Signal Clock Clock Phase DCLK=0 00 ICLK In phase QCLK In phase DCLK=1 01 QCLK In phase ICLK In phase DCLK=2 10 ICLK 180° out of phase QCLK 180° out of phase DCLK=3 11 QCLK 180° out of phase ICLK 180° out of phase 7.2.13 PGA Voltage Gain Control (Address 0x27/0x37) The 0x37 command sets the PGA voltage gain. This 3-bit number (PGA [2:0]) adjusts the input voltage level to the ADC to optimize its conversion resolution. The 0x27 command reads the PGA value. At power-up, PGA defaults to 0x00.The PGA is defined as an inverted amplifier. Figure 37: PGA Settings PGA Value PGA [2:0] Binary Read/Write PGA Gain PGA_0 000 R/W 36 PGA_1 001 R/W 24 PGA_2 010 R/W 16 PGA_3 011 R/W 10.67 PGA_4 100 R/W 7.11 PGA_5 101 R/W 4.74 PGA_6 110 R/W 3.16 |
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