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TSL25213 数据表(PDF) 29 Page - OSRAM GmbH |
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TSL25213 数据表(HTML) 29 Page - OSRAM GmbH |
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29 / 81 page ![]() Page 28 Datasheet, Public Document Feedback [v3-00] 2022-Dec-21 TSL2521 − Register O ver view STATUS Register Figure 32: STATUS Note(s): 1. Return to the Register Map (0x93). Addr: 0x93 STATUS Bit Field Reset Type Bit Description 7MINT 0 R/W Modulator Interrupt: Indicates that a modulator interrupt has occurred because of saturation. Check the STATUS2 register to differentiate between analog or digital saturation. Writing 1 to this bit clear MINT and all subsequent interrupts. 6:4 Reserved 0 3AINT 0 R/W ALS Interrupt. If AIEN is set, this interrupt indicates that an ALS event that met the programmed ALS thresholds (AILT or AIHT) and persistence (APERS) occurred. Check the STATUS3 register to differentiate. Writing 1 to this bit clear AINT and all subsequent interrupts. 2FINT 0 R/W FIFO Interrupt. Indicates that the data level in the FIFO met the programmed FIFO thresholds (FIFO_LVL and FIFO_THR). This interrupt is automatically asserted/removed depending on the programmed FIFO thresholds. Writing 1 to this bit clears FINT. The interrupt, however, will be promptly asserted again in case the FIFO has not been read out or cleared. 1Reserved 0 0SINT 0 R/W System Interrupt. If SIEN is set, indicates that one or more of several events has occurred or is complete. The events related to this interrupt are indicated in the STATUS5 register. |
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