Page 18

ams Datasheet

Document Feedback

[v1-01] 2018-Apr-23

TSL2561 − Principles of Operation

Figure 19:

Interrupt Threshold Register

Note(s):

1. Since two 8-bit values are combined for a single 16-bit value for each of the high and low interrupt thresholds, the Send Byte protocol

should not be used to write to these registers. Any values transferred by the Send Byte protocol with the MSB set would be interpreted

as the COMMAND field and stored as an address for subsequent read/write operations and not as the interrupt threshold information

as desired. The Write Word protocol should be used to write byte-paired registers. For example, the THRESHLOWLOW and

THRESHLOWHIGH registers (as well as the THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the

16-bit ADC value in a single transaction.

Interrupt Control Register (6h)

The Interrupt Register controls the extensive interrupt

capabilities of the TSL2561.The interrupt persist bit field

(PERSIST) provides control over when interrupts occur. A value

of 0 causes an interrupt to occur after every integration cycle

regardless of the threshold settings. A value of 1 results in an

interrupt after one integration time period outside the

threshold window. A value of N (where N is 2 through15) results

in an interrupt only if the value remains outside the threshold

window for N consecutive integration cycles. For example, if N

is equal to 10 and the integration time is 402ms, then the total

time is approximately 4 seconds.

When a level Interrupt is selected, an interrupt is generated

whenever the last conversion results in a value outside of the

programmed threshold window. The interrupt is active-low and

remains asserted until cleared by writing the Command

Register with the CLEAR bit set.

Note(s): Interrupts are based on the value of Channel 0 only.

Figure 20:

Interrupt Control Register

Register

Address

Bits

Description

THRESHLOWLOW

2h

7:0

ADC channel 0 lower byte of the low threshold

THRESHLOWHIGH

3h

7:0

ADC channel 0 upper byte of the low threshold

THRESHHIGHLOW

4h

7:0

ADC channel 0 lower byte of the high threshold

THRESHHIGHHIGH

5h

7:0

ADC channel 0 upper byte of the high threshold

7

6

5432

10

Resv

Resv

INTR

PERSIST

Field

Bits

Description

Resv

7:6

Reserved. Write as 0.

INTR

5:4

INTR Control Select. This field determines mode of interrupt logic according to

Figure 21, below.