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AS6221

Register Description

Datasheet

• PUBLIC

DS000751

• v3-00 • 2022-Feb-28

38

│ 28

A transition of the SDA input from high to low level while the SCL signal is kept at high level results in

a START condition. Such a START condition must precede any data transfer.

Stop Data Transfer

A transition of the SDA input from low to high level while the SCL signal is kept at high level results in

a STOP condition. Any data transfer is finished by generating a STOP or START condition.

Data Transfer

The master device defines the number of data bytes between a START and STOP condition and there

is no limitation in the amount of data to be transmitted.

If it is desired to read only a single MSB byte without the LSB byte, a termination of the data transfer

can be provoked by issuing a START or STOP condition on the bus.

Acknowledge

It is mandatory for each slave device to respond with acknowledge if the device is addressed by the

master. Acknowledge is indicated by pulling down the data line (SDA) while the clock signal (SCL) is

high in the acknowledge clock phase. In order to avoid an unwanted START or STOP condition on the

bus, setup and hold times must be met.

The master can signal an end of data transmission by transmitting a Not-Acknowledge on the last

transmitted data byte by keeping the acknowledge bit at high level.

6.3.14

Timing Characteristics

Figure 30:

Serial Interface Timing Diagram