MPC8323VRADDC datasheet(43/80 Pages) FREESCALE

部件名	MPC8323VRADDC

功能描述	PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications

PDF	80 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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43 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

HDLC, BISYNC, Transparent, and Synchronous UART

Figure 35 provides the AC test load for the UTOPIA.

Figure 35. UTOPIA AC Test Load

Figure 36 and Figure 37 represent the AC timing from Table 49. Note that although the specifications

generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge

is the active edge.

Figure 36 shows the UTOPIA timing with external clock.

Figure 36. UTOPIA AC Timing (External Clock) Diagram

Figure 37 shows the UTOPIA timing with internal clock.

Figure 37. UTOPIA AC Timing (Internal Clock) Diagram

19 HDLC, BISYNC, Transparent, and Synchronous

UART

This section describes the DC and AC electrical specifications for the high level data link control (HDLC),

BISYNC, transparent, and synchronous UART of the MPC8323E.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

UTOPIACLK (Input)

tUEIXKH

tUEIVKH

tUEKHOV

Input Signals:

UTOPIA

Output Signals:

UTOPIA

tUEKHOX

UTOPIACLK (Output)

tUIIXKH

tUIKHOV

Input Signals:

UTOPIA

Output Signals:

UTOPIA

tUIIVKH

tUIKHOX

MPC8323VRADDC 数据表(PDF) 43 Page - Freescale Semiconductor, Inc

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