| 数据搜索系统,热门电子元器件搜索 |
|
SN74LVC00ADE4 数据表(PDF) 12 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
SN74LVC00ADE4 数据表(HTML) 12 Page - Texas Instruments |
|
12 / 39 page ![]() 8.2.3 Application Curve Figure 8-2. ICC vs Frequency Power Supply Recommendations The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 5.4 table. Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 µF is recommended; if there are multiple VCC pins, then 0.01 µF or 0.022 µF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and a 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results. 8.3 Layout 8.3.1 Layout Guidelines When using multiple bit logic devices inputs should never float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Section 8.3.2 specifies the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs, unless the part is a transceiver. 8.3.2 Layout Example 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1A 1B 2A 2B 2Y GND V CC 4B 4A 3B 3A 3Y GND V CC 4Y 1Y 0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 8-3. Layout Diagram for the SNx4LVC00A SN54LVC00A, SN74LVC00A SCAS279S – JANUARY 1993 – REVISED MARCH 2024 www.ti.com 12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: SN54LVC00A SN74LVC00A |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |