AD5522JSVD datasheet(21/48 Pages) AD

21 / 48 page

Preliminary Technical Data

AD5522

Rev. PrM | Page 21 of 48

GUARD AMPLIFER

A Guard amplifier allows the user to bootstrap the shield of the

cable to the voltage applied to the DUT, ensuring minimal

drops across the cable. This is particularly important for

measurements requiring a high degree of accuracy and in

leakage current testing.

If not required, all four Guard Amplifiers may be disabled via

the serial interface (through the System Control Register), this

decreases the power consumption by 400uA per channel.

As described in the DUTGND section, the GUARDIN(0-3)

/DUTGND(0-3) is a shared pin. It can function either as a

guard amplifier input per channel or as a DUTGND input per

channel as required by the end application. Refer to Figure 20.

A Guard alarm event occurs when the guard output moves

more than 100mV away from the Guard input voltage for more

than 200μs. In the event this happens, this will be flagged via

the CGALM open drain output. As the guard and clamp alarm

functions share the same alarm outputCGALM, the alarm

information (alarm trigger and alarm channel) is available via

the serial interface (ALARM STATUS REGISTER).

Alternatively, the serial interfaces allow the user to setup the

CGALM output to flag either the clamp status or the guard

status. By default, this open drain alarm pin is an unlatched

output, but may be set to a latched output via the serial

interface, System Control Register.

COMPENSATION CAPACITORS

Each channel requires an external compensation capacitor

(CCOMP) to ensure stability into the maximum load capacitance

while ensuring settling time is optimized. In addition, one CFF

pin is provided to further optimize stability and settling time

performance when in Force voltage mode. When changing

from Force current to force voltage mode, the switch

connecting CFF capacitor is automatically closed. While the

force amplifier is designed to drive load capacitances up to 10nF

(with Ccomp = 100pF), using larger compensation capacitor

values, it is possible to drive larger load at the expense of an

increase in settling time. If a wide range of load capacitance

must be driven, then an external multiplexer connected to the

CCOMP pin will allow optimization of settling time versus

stability. The series resistance of a switch placed on CCOMP,

should typically be <50Ω.

Similarly, connecting the CFF node to a multiplexer externally,

would cater for a wide range of CDUT in Force Voltage mode.

The series resistance of the multiplexer used should be such

that:

kHz

CDUT

RON

100

⎟

⎠

⎞

⎜

⎝

⎛

Table 9. Suggested Compensation Capacitor Selection

CLOAD

CCOMP

CFF

≤1nF

100pF

220pF

≤10nF

100pF

1nF

≤100nF

CLOAD/100

CLOAD/10

AD5522JSVD 数据表(PDF) 21 Page - Analog Devices

AD5522JSVD 数据表(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载