AD9516-3SLASHPCBZ datasheet(13/84 Pages) AD

13 / 84 page

AD9516-3

Rev. 0 | Page 13 of 84

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHI

Pulse Width Low, tLO

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

1.1

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, tPWH

PD, SYNC, AND RESET PINS

Table 15.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT CHARACTERISTICS

These pins each have a 30 kΩ internal pull-up resistor

Logic 1 Voltage

2.0

Logic 0 Voltage

0.8

Logic 1 Current

110

μA

Logic 0 Current

μA

Capacitance

RESET TIMING

Pulse Width Low

SYNC TIMING

Pulse Width Low

1.5

High speed clock cycles

High speed clock is CLK input signal

LD, STATUS, REFMON PINS

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS); there are other

modes in which these pins are not CMOS digital outputs;

see Table 53, 0x17, 0x1A, and 0x1B

Output Voltage High (VOH)

2.7

Output Voltage Low (VOL)

0.4

MAXIMUM TOGGLE RATE

100

MHz

Applies when mux is set to any divider or counter output,

or PFD up/down pulse; also applies in analog lock detect

mode; usually debug mode only; beware that spurs may

couple to output when any of these pins are toggling

ANALOG LOCK DETECT

Capacitance

On-chip capacitance; used to calculate RC time constant

for analog lock detect readback; use a pull-up resistor

REF1, REF2, AND VCO FREQUENCY STATUS MONITOR

Normal Range

1.02

MHz

Frequency above which the monitor indicates the

presence of the reference

Extended Range

kHz

Frequency above which the monitor indicates the

presence of the reference

LD PIN COMPARATOR

Trip Point

1.6

Hysteresis

260

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